Structure with isotropic silicon recess profile in nanoscale dimensions

ABSTRACT

A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/561,704, filed on Sep. 17, 2009 the entire content and disclosure ofwhich is incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with United States government support underContract No. FA8650-08-C-7806 awarded by Defense Advanced ResearchProjects Agency (DARPA). The United States government has certain rightsin this invention.

BACKGROUND

This invention relates to methods of laterally offsetting sidewalls of atrench in a semiconductor substrate relative to sidewalls of overlyingstructures and structures formed by the same.

Etching in a vertical direction is an integral component ofsemiconductor processing technology. An isotropic etch employs wetchemicals or reactant gases that etch a material isotropically. The etchrate of isotropic etch processes are difficult to control on ananoscale, i.e., on a scale from 0.1 nm to 10 nm, because the etch rateis sensitive to temperature and/or supply of etchant.

Plasma processing provides a more precise control of the etch rate.Plasma etch chambers are designed to etch anisotropically in a verticaldirection. Advanced semiconductor chips require a high degree of profilecontrol, where the extent of vertical etching may be difficult tocontrol. The ion energy due to the plasma self-bias potential is theultimately lowest ion energy attainable in plasma reactors, while stillenabling a reasonable degree of vertical etching.

Known plasma-etch-based solutions to recessing silicon on a nanoscalegenerate a post-etch profile in which lateral silicon erosion in thehorizontal direction can be up to about ⅓ of the silicon erosion in thevertical direction, i.e., in the direction of the impinging plasma. Theamount of lateral etching relative to the depth of a trench formed by aplasma etch is limited. This constraint makes it difficult to enableuseful features in semiconductor technology such as tunnel field effecttransistor (FET) having strained semiconductor-on-insulator (SSOI)features, which may be a crucial component in obtaining sub-thresholdslope characteristics below the classical limit of 60 mV/decade.

BRIEF SUMMARY

In an embodiment of the present invention, a trench is formed by ananisotropic etch in a semiconductor material layer employing a maskinglayer. An adsorbed fluorine layer is formed on the exposed surfaces of asemiconductor structure including the bottom surface and the sidewallsof the trench at a cryogenic temperature. A sputtering process performedat a cryogenic temperature removes horizontal portions of the adsorbedfluorine layer so that the remaining adsorbed fluorine layer is presentonly on vertical sidewalls of the semiconductor structure including thesidewalls of the trench. The temperature of the semiconductor structureis raised above the cryogenic temperature to enable reaction of theadsorbed fluorine layer with the semiconductor material in a lateraldirection. The adsorbed fluorine layer removes a controlled amount ofthe underlying semiconductor material by chemically reacting andremoving the semiconductor material. The amount of removal of thesemiconductor material is in the range of monolayers of thesemiconductor material, thereby providing a lateral etch by a nanoscaledimension.

In another embodiment of the present invention, a trench is formed by ananisotropic etch in a semiconductor material layer employing a maskinglayer, which can be gate spacers. The crystallographic orientations ofthe sidewalls of the trench are selected to provide a lower oxidationrate than the crystallographic orientation of the bottom surface of thetrench. A contiguous oxide liner having a thicker bottom portionrelative to thinner sidewall portions is formed by oxidation. Thecontiguous oxide liner is isotropically etched to remove the thinnersidewall portions. The semiconductor material is laterally etched by aplasma-based etch at a controlled rate in a chemistry that is somewhatselective to the oxide layer atop the horizontal surface, therebypreventing etch of the semiconductor material underneath the oxidelayer. The remaining horizontal portion of the contiguous oxide issubsequently removed, and the trench can be filled with a differentsemiconductor material to provide stress to neighboring semiconductorregions, which can include a channel of a field effect transistor.

According to an aspect of the present invention, a method of forming asemiconductor structure is provided. The method includes forming atrench in a semiconductor material layer, and forming an adsorbedfluorine layer on vertical surfaces of the trench, while horizontalsurfaces of the trench do not have adsorbed fluorine thereupon.

According to another aspect of the present invention, another method offorming a semiconductor structure is provided. The method includesforming a trench in a semiconductor material layer; forming a contiguoussemiconductor oxide liner on sidewalls and a bottom surface of thetrench; exposing sidewall surfaces of the trench by removing verticalportions of the contiguous semiconductor oxide liner while a remaininghorizontal semiconductor oxide portion of the contiguous semiconductoroxide liner overlies a portion of the semiconductor material layerlocated underneath the trench; and laterally etching the sidewallsurfaces of the trench while the remaining horizontal semiconductoroxide portion covers the portion of the semiconductor material layerlocated underneath the trench.

According to yet another aspect of the present invention, asemiconductor structure is provided. The semiconductor structureincludes a gate structure located on a semiconductor material layerincluding a first semiconductor material, the gate structure including agate dielectric, a gate conductor, and a gate spacer; a semiconductormaterial portion embedded in the semiconductor material layer, thesemiconductor material portion including a second semiconductor materialthat is different from the first semiconductor material; and anon-planar interface region between the first semiconductor material andthe second semiconductor material, wherein the non-planar interfaceregion includes a first horizontal interface portion at a first depthfrom the gate dielectric, a second horizontal interface portion at asecond depth from the gate dielectric, and a non-horizontal interfaceportion adjoined to the first horizontal interface portion and thesecond horizontal interface portion and underlying the gate spacer.

According to still another aspect of the present invention, anothersemiconductor structure is provided. The semiconductor structureincludes a trench in a semiconductor material layer; and an adsorbedfluorine layer located on vertical surfaces of the trench, whilehorizontal surfaces of the trench do not have adsorbed fluorinethereupon.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a vertical cross-sectional view of a first exemplary structurebefore formation of a trench according to a first embodiment of thepresent invention.

FIG. 2 is a vertical cross-sectional view of the first exemplarystructure after forming a trench according to the first embodiment ofthe present invention.

FIG. 3 is a vertical cross-sectional view of the first exemplarystructure after forming a contiguous adsorbed fluorine layer accordingto the first embodiment of the present invention.

FIG. 4 is a vertical cross-sectional view of the first exemplarystructure after removal of horizontal portions of the contiguousadsorbed fluorine layer to provide adsorbed fluorine layer present onlyon vertical surfaces according to the first embodiment of the presentinvention.

FIG. 5 is a vertical cross-sectional view of the first exemplarystructure after lateral etching of the sidewalls of the trench accordingto the first embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view of the first exemplarystructure after formation of an embedded semiconductor material portionaccording to the first embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view of a second exemplarystructure after forming a contiguous semiconductor oxide liner accordingto a second embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view of the second exemplarystructure after removing vertical portions of the contiguoussemiconductor oxide liner according to the second embodiment of thepresent invention.

FIG. 9 is a vertical cross-sectional view of the second exemplarystructure after laterally etching a semiconductor material employing ahorizontal semiconductor oxide portion according to the secondembodiment of the present invention.

FIG. 10 is a vertical cross-sectional view of the second exemplarystructure after removing the horizontal semiconductor oxide portionaccording to the second embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view of the second exemplarystructure after formation of an embedded semiconductor material portionaccording to the second embodiment of the present invention.

FIG. 12 is a vertical cross-sectional view of a variation of the secondexemplary structure after formation of an embedded semiconductormaterial portion according to the second embodiment of the presentinvention.

DETAILED DESCRIPTION

As stated above, the present invention relates to methods of laterallyoffsetting sidewalls of a trench in a semiconductor substrate relativeto sidewalls of overlying structures and structures formed by the same,which are now described in detail with accompanying figures. Thedrawings are not necessarily drawn to scale.

Referring to FIG. 1, a first exemplary structure according to a firstembodiment of the present invention includes a substrate 8, a first gatestructure 20A located on a top surface of the substrate 8, and a secondgate structure 20B located on the top surface of the substrate 8 andlaterally spaced from the first gate structure 20A. The substrate 8includes a semiconductor material layer 10, which is comprised of asemiconductor material. The semiconductor material of the semiconductormaterial layer 10 can be selected from, but is not limited to, silicon,germanium, silicon-germanium alloy, silicon carbon alloy,silicon-germanium-carbon alloy, gallium arsenide, indium arsenide,indium phosphide, III-V compound semiconductor materials, II-VI compoundsemiconductor materials, organic semiconductor materials, and othercompound semiconductor materials. Preferably, the semiconductor materialof the semiconductor material layer 10 is a single crystalline material.For example, the semiconductor material layer 10 can be a singlecrystalline silicon layer. The substrate 8 may include a buriedinsulator layer 9. Further, the substrate 8 may include a handlesubstrate (not shown) located beneath the buried insulator layer 9, ifpresent.

The first gate structure 20A can include a first gate dielectric 22A, afirst gate conductor 24A, a first gate spacer 26A, and a firstdielectric cap 28A. The second gate structure 20B can include a secondgate dielectric 22B, a second gate conductor 24B, a second gate spacer26B, and a second dielectric cap 28B. The first and second gatedielectrics (22A, 22B) can be a silicon-oxide-based gate dielectricmaterial or a high dielectric constant (high-k) dielectric material suchas a dielectric metal oxide, having a dielectric constant greater than4.0. The first and second gate conductors (24A, 24B) can be a dopedsemiconductor material, a metallic material, or a combination thereof.The first and second gate dielectrics (26A, 26B) can be a dielectricmaterial such as silicon nitride, silicon oxynitride, or a combinationof silicon oxide and silicon nitride. Preferably, the outer surfaces ofthe first and second gate dielectrics (26A, 26B) include a semiconductornitride or a semiconductor oxynitride such as silicon nitride or siliconoxynitride. The first and second dielectric caps (28A, 28B) can be adielectric material such as silicon nitride, silicon oxynitride, or acombination of silicon oxide and silicon nitride. Preferably, the topsurfaces of the first and second dielectric caps (28A, 28B) include asemiconductor nitride or a semiconductor oxynitride such as siliconnitride or silicon oxynitride.

Referring to FIG. 2, a trench 30 is formed by etching an exposed portionof the semiconductor material layer 10 between the first and second gatestructures (20A, 20B). The trench 30 can be formed by an anisotropicetch that etches the semiconductor material of the semiconductormaterial layer 10 selective to the dielectric materials of the first andsecond gate spacers (26A, 26B) and the first and second dielectric caps(28A, 28B). If the buried insulator layer 9 is present, the depth of thetrench 30 is selected to be less than the depth of the buried insulatorlayer 9. The trench 30 has a bottom surface and sidewalls. The bottomsurface of the trench 30 is a horizontal surface, and the sidewalls ofthe trench 30 are typically substantially vertical. The periphery of thesidewalls of the trench 30 can coincide with outer peripheries of thefirst and second gate spacers (26A, 26B) at which the outer sidewalls ofthe first and second gate spacers (26A, 26B) contact a top surface ofthe semiconductor material layer 10.

Referring to FIG. 3, the first exemplary structure is placed in acryogenic environment, which has an ambient temperature below −40degrees Celsius, and preferably below −100 degrees Celsius. Placement ofthe first exemplary structure in a cryogenic environment can be effectedby providing a cryogenic chamber and inserting the first exemplarystructure into the cryogenic chamber. Preferably, the cryogenic chamberis a vacuum enclosure that provides a cryogenic temperature and lowresidual gas pressure.

After the first exemplary structure is cooled below −40 degrees Celsius,and preferably below −100 degrees Celsius, the cryogenic chamber isfilled with a fluorine-containing gas. The fluorine-containing gasincludes any gas that contains fluorine atoms that adsorb to a surfaceat a cryogenic temperature. For example, the fluorine-containing gas canbe, but is not limited to F₂, CClF₃, CF₄, SF₆, XeF₂, CHF₃, CH₂F₂, CH₃F,C₄F₆, C₅F₈, C₄F₈ or any combination thereof. A contiguous adsorbedfluorine layer 80 is formed on exposed surfaces of the first exemplarysemiconductor structure at the cryogenic temperature because thefluorine-containing gas is adsorbed on the cold surfaces of the firstexemplary structure. The surfaces on which the contiguous adsorbedfluorine layer 80 is formed include the bottom surface and the sidewallsof the trench 30. Typically, the contiguous adsorbed fluorine layer 80contiguously extends over all of the exposed surfaces of the firstexemplary semiconductor structure without a hole or a discontinuity.Thus, the contiguous adsorbed fluorine layer 80 is formed on allsurfaces of the trench 30, i.e., on horizontal and vertical surfaces ofthe trench 30. The contiguous adsorbed fluorine layer 80 can be amonolayer of fluorine atoms that are atomically bonded to an underlyingsemiconductor material in the semiconductor material layer 10.

Referring to FIG. 4, horizontal portions of the contiguous adsorbedfluorine layer 80 are removed to provide adsorbed fluorine layers 82that are present only on vertical surfaces of the first exemplarysemiconductor structure. For example, the cryogenic chamber can beequipped with sputtering capability to provide ions that impinge uponthe first exemplary structure in a direction that is substantiallynormal to the bottom surface 31 of the trench 30. Ions that can beemployed to sputter and remove horizontal portions of the contiguousadsorbed fluorine layer 80 include, but are not limited to, Kr, He, Ne,Ar, Xe, H₂, N₂, and O₂. The ion sputtering destroys the chemical bondingbetween the adsorbed atoms and the underlying semiconductor material sothat the horizontal surface of the trench 30 does not have adsorbedfluorine thereupon after the sputtering. Horizontal portions of thecontiguous adsorbed fluorine layer 80 are thus removed, and verticalportions of the contiguous adsorbed fluorine layer 80 remain toconstitute the adsorbed fluorine layers 82, which cover all of thevertical sidewalls of the trench 30 and a lower portion of the outersidewalls of the first and second gate spacers (26A, 26B). Each of theadsorbed fluorine layers 82 contiguously extends over a vertical portionof an outer surface of one of the first and second gate spacers (26A,26B). Preferably, the sputtering is performed at a cryogenic temperaturebelow −40 degrees Celsius, and preferably below −100 degrees Celsius.

Alternately, the sputtering can be performed in another cryogenicchamber after transporting the first exemplary semiconductor structureinto the other cryogenic chamber. Preferably, the ambient conditions ofthe first exemplary structure is maintained at a cryogenic temperatureand in vacuum or in an inert ambient to prevent the contiguous adsorbedfluorine layer 80 from becoming volatile. After transfer of the firstexemplary structure into the other chamber, ions impinge upon the firstexemplary structure in a direction that is substantially normal to thebottom surface 31 of the trench 30 to remove the horizontal portions ofthe contiguous adsorbed fluorine layer 80. The remaining verticalportions of the contiguous adsorbed fluorine layer 80 constitute theadsorbed fluorine layers 82, which cover all of the vertical sidewallsof the trench 30 and a lower portion of the outer sidewalls of the firstand second gate spacers (26A, 26B). The horizontal bottom surface of thetrench 30 does not have adsorbed fluorine thereupon. Each of theadsorbed fluorine layers 82 contiguously extends over a vertical portionof an outer surface of one of the first and second gate spacers (26A,26B). Preferably, the sputtering is performed at a cryogenic temperaturebelow −40 degrees Celsius, and preferably below −100 degrees Celsius.

Referring to FIG. 5, the temperature of the first exemplary structure israised above −40 degrees Celsius. For example, the first exemplarystructure may be exposed to an ambient at a room temperature between 5degrees Celsius and 35 degrees Celsius. As the temperature of the firstexemplary structure is raised, the sidewalls of the trench 30 arelaterally etched by the adsorbed fluorine layers 82. Specifically, theadsorbed fluorine layers 82 and the vertical surfaces of the trench 30are subjected to a temperature at which the adsorbed fluorine layers 82etch the underlying semiconductor material on the vertical surfaces ofthe trench 80 by reacting with the underlying semiconductor material ofthe semiconductor material layer 10. The amount of etched semiconductormaterial is measured in monolayers, and is typically from 1 to 4 atomiclayers of the semiconductor material in the semiconductor material layer10. Thus, the lateral recess width RW is from 0.3 nm to 1.5 nm dependingon the crystallographic orientation of the semiconductor material at thesidewalls of the trench 30.

Referring to FIG. 6, an embedded semiconductor material portion 50 isformed by filling the trench 30 with another semiconductor material,which is typically a different material than the semiconductor materialof the semiconductor material layer 10. The semiconductor material ofthe embedded semiconductor material portion 50 can generate mechanicalstress in a portion of the semiconductor material layer 10 locatedaround the embedded semiconductor material portion 50.

The semiconductor material of the semiconductor material layer 10 andthe semiconductor material of the embedded semiconductor materialportion 50 can be single crystalline semiconductor materials that areepitaxially aligned to each other. The material of the embeddedsemiconductor material portion can be selected from, but is not limitedto, a single crystalline silicon-germanium alloy, a single crystallinesilicon-carbon alloy, and a single crystalline silicon-germanium-carbonalloy. The vertical interfaces between the semiconductor material layer10 and the embedded semiconductor material portion 50 are laterallyoffset by the lateral recess width RW from outer peripheries of thefirst and second gate spacers (26A, 26B) at which the first and secondgate spacers (26A, 26B) contact the embedded semiconductor materialportion 50.

A second exemplary structure according to a second embodiment of thepresent invention is derived from the first exemplary structure in FIG.2 according to the first embodiment of the present invention. In thesecond exemplary structure, a limitation is imposed on thecrystallographic orientation of the bottom surface of the trench 30 andthe crystallographic orientations of the sidewalls of the trench 30 at astep corresponding to FIG. 2. Specifically, the bottom surface of thetrench 30 has a crystallographic orientation that provides a greateroxidation rate for the semiconductor material of the semiconductormaterial layer 10 than crystallographic orientations of the sidewalls ofthe trench 30. For example, if the semiconductor material layer 10 is asingle crystalline silicon layer and the bottom surface of the trench 30has a <111> orientation, and the sidewall surfaces of the trench 30 canhave <110> orientation. Alternately, if the semiconductor material layer10 is a single crystalline silicon layer and the bottom surface of thetrench 30 has a <110> orientation, and the sidewall surfaces of thetrench 30 can have a <100> orientation. In general, any combination ofcrystallographic orientations for the bottom surface and sidewalls ofthe trench 30 can be employed as long as the bottom surface of thetrench 30 has a higher oxidation rate than the sidewalls of the trench30. Alternatively, the bottom of said trench can by oxidized to agreater depth than the sidewalls by exposing the structure to an oxygenplasma, where the ion energy is greater than the plasma potential alone.Due to the geometry of the reactor, high energy ions will react with thebottom trench forming an oxide of thickness t1, whereas the sidewalls ofthe trench only react with plasma neutrals and scattered ions, forming athinner oxide of thickness t2. Gate structures can be masked during thisprocess. In this case, the crystallographic orientation of the bottomsurface of the trench need not have a greater oxidation rate for thermaloxidation than sidewall surfaces of the trench because the geometryemployed in the plasma oxidation induces greater oxidation rate on thebottom surfaces of the trench than on the sidewall surfaces of thetrench.

Referring to FIG. 7, after a trench 30 is formed in the semiconductormaterial layer 10 of the second exemplary structure at a stepcorresponding to FIG. 2, a contiguous semiconductor oxide liner 40 isformed on all exposed surfaces of the trench 30 including the sidewallsand the bottom surface of the trench 30. The contiguous semiconductoroxide liner 40 is formed by converting the semiconductor material in thesemiconductor material layer 10 into a semiconductor oxide. For example,if the semiconductor material in the semiconductor material layer 10 issilicon, the semiconductor oxide is silicon oxide. Because of thedifferential between the oxidation rates of the bottom surface andsidewalls of the trench 30, the first thickness t1 of the horizontalportion of the contiguous semiconductor oxide liner 40 is greater thanthe second thickness t2 of the vertical portions of the contiguoussemiconductor oxide liner 40.

Referring to FIG. 8, vertical portions of the contiguous semiconductoroxide liner 40 are removed, for example, by an isotropic etch. Theisotropic etch can be a wet etch or a dry etch. In case a wet etch isemployed, a dilute hydrofluoric acid can be employed to provide a slowetch rate if the contiguous semiconductor oxide liner 40 includessilicon oxide, a germanium oxide, or silicon-germanium oxide. In casethe isotropic etch is a dry etch, an etchant gas such as HCl, SF₆, XeF₂,CF₄ or NF₃ can be employed.

The duration of the etch is controlled so that the amount of removal ofthe contiguous semiconductor oxide liner 40 is greater than the secondthickness t2 and is lesser than the first thickness t1. Thus, sidewallsurfaces 33 of the trench are exposed as vertical portions of thecontiguous semiconductor oxide liner 40 are removed by the etch process.A remaining horizontal semiconductor oxide portion of the contiguoussemiconductor oxide liner 40, which is herein referred to as ahorizontal semiconductor oxide portion 42, overlies the portion of thesemiconductor material layer 10 located underneath the trench 42. Edgesof the horizontal semiconductor oxide portion 42 contact the sidewallsurfaces 33 of the trench 30 at this step.

Referring to FIG. 9, the exposed semiconductor material on the sidewallsurfaces 33 of the trench 30 is laterally etched while the horizontalsemiconductor oxide portion 42 covers the portion of the semiconductormaterial layer 10 located underneath the trench 30, thereby preventingetching of the semiconductor material underneath the bottom surface ofthe trench 30. The sidewall surfaces 33 of the trench 30 can belaterally etched by a dry etch or a wet etch. Preferably, the sidewallsurfaces 33 of the trench 30 are laterally etched by a plasma etch,which is a dry etch. In case a plasma etch is employed to etch thesidewall surfaces 33 of the trench 30, the etch process can benefit froma precision control of the etch rate and enhanced uniformity of the etchrate, which are typically associated with the plasma etch. The sidewallsurfaces 33 of the trench 30 are laterally etched while the horizontalsemiconductor oxide portion 42 remains at the bottom of the trench 30.Because the lateral etch makes the sidewall surfaces 33 of the trenchrecede from the original positions as the etch progresses, thehorizontal semiconductor oxide portion 42 does not cover a peripheralportion of the bottom surface of the trench 30 as the lateral etchprogresses.

Referring to FIG. 10, the horizontal semiconductor oxide portion 42 isremoved to expose the portion of the semiconductor material layer 10located underneath. The horizontal semiconductor oxide portion 42 can beremoved selective to the semiconductor material layer 10. For example,if the horizontal semiconductor oxide portion 42 includes silicon oxide,germanium oxide, or a silicon-germanium oxide, the horizontalsemiconductor oxide portion 42 can be removed by a wet etch employing ahydrofluoric acid (HF) solution or a dry etch employing HF in a vaporphase.

The center portion of the trench 30 can have a first depth D1, and theperipheral portions of the trench 30 can have a second depth D2. Thecentral portion of the trench 30 corresponds to the area over which thehorizontal semiconductor oxide portion 42 is present during the lateraletch of the trench 30. The peripheral portions of the trench correspondsto the area over which the horizontal semiconductor oxide portion 42 isnot present during the lateral etch of the trench 30. When the firstdepth D1 is not the same as the second depth D2, a first non-planarsurface region 62A is formed on the side of the first gate stack 20A,and a second non-planar surface region 62B is formed on the side of thesecond gate stack 20B. Each of the first and second non-planar surfaceregions (62A, 62B) includes a sub-region having the first depth D1 and asub-region having the second depth D2.

Referring to FIG. 11, an embedded semiconductor material portion 50 isformed by filling the trench 30 with another semiconductor material,which is typically a different material than the semiconductor materialof the semiconductor material layer 10. The semiconductor material ofthe embedded semiconductor material portion 50 can generate mechanicalstress in a portion of the semiconductor material layer 10 locatedaround the embedded semiconductor material portion 50.

The semiconductor material of the semiconductor material layer 10 andthe semiconductor material of the embedded semiconductor materialportion 50 can be single crystalline semiconductor materials that areepitaxially aligned to each other. The material of the embeddedsemiconductor material portion can be selected from, but is not limitedto, a single crystalline silicon-germanium alloy, a single crystallinesilicon-carbon alloy, and a single crystalline silicon-germanium-carbonalloy.

The embedded semiconductor material portion 50 contacts thesemiconductor material layer 10 at a first horizontal interface locatedat the first depth D1 from the first and second gate dielectrics (22A,22B) and at a second horizontal interface located at the second depth D2from the first and second gate dielectrics (22A, 22B). A firstnon-planar interface region 63A is formed on the side of the first gatestack 20A, and a second non-planar interface region 63B is formed on theside of the second gate stack 20B. Each of the first and secondnon-planar interface regions (63A, 63B) includes a portion of a firsthorizontal interface, i.e., a “first horizontal interface portion,” aportion of a second horizontal interface, i.e., a “second horizontalinterface portion,” and a non-horizontal interface portion adjoined tothe first horizontal interface portion and the second horizontalinterface portion. The first non-planar interface region 63A underliesthe first gate spacer 26A, and the second non-planar interface region63B underlies the second gate spacer 26B.

Further, the embedded semiconductor material portion 50 contacts thesemiconductor material layer 10 at a first vertical interface locatedunderneath the first gate spacer 26A and at second vertical interfacelocated underneath the second gate spacer 26B. In other words, the firstvertical interface underlies the first gate spacer 26A, and the secondvertical interface underlies the second gate spacer 26B.

Referring to FIG. 12, a variation of the second exemplary structure isshown, in which the first vertical interface and the second verticalinterface between the embedded semiconductor material portion 50contacts the semiconductor material layer 10 can be moved further fromthe outer peripheries of the first and second gate spacers (26A, 26B).The lateral offset LO is the most proximal lateral distance between eachof the first and second vertical interfaces and the outer peripheries ofthe first and second gate spacers (26A, 26) at which the first andsecond gate spacers contact the embedded semiconductor material portion50. The lateral offset LO can be increased by increasing the time periodof the lateral etch of the sidewall surfaces 33 of the trench 30 at astep corresponding to FIG. 9.

In the variation of the second exemplary structure, the lateral offsetLO is greater than the lateral width of the bottom portions of the firstand second gate spacers (26A, 26B). Correspondingly, the first verticalinterface underlies the first gate dielectric 22A, and the secondvertical interface underlies the second gate dielectric 22B. Theembedded semiconductor material portion 50 contacts bottom surfaces ofthe first and second gate dielectrics (22A, 22B).

The present invention can be practiced with any number of gatestructures or without any gate structure. Further, shallow trenchisolation structures including a dielectric material can be employed ineach of the first and second exemplary structures.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details can be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A semiconductor structure comprising: a trench located in asemiconductor material layer; and an adsorbed fluorine layer located onvertical surfaces of said trench, while horizontal surfaces of saidtrench do not have adsorbed fluorine thereupon.
 2. The semiconductorstructure of claim 1, wherein said semiconductor material layercomprises silicon.
 3. The semiconductor structure of claim 1, whereinsaid adsorbed fluorine layer is a monolayer of fluorine atoms that areatomically bonded to an underlying semiconductor material in saidsemiconductor material layer.
 4. The semiconductor structure of claim 1,further comprising a gate structure located on said semiconductormaterial layer, said gate structure including a gate dielectric, a gateconductor, and a gate spacer.
 5. The semiconductor structure of claim 4,wherein said adsorbed fluorine layer contiguously extends over avertical portion of a surface of said gate spacer.
 6. The semiconductorstructure of claim 1, wherein said vertical surfaces define a peripheryof said trench, and said adsorbed fluorine layer contiguously covers allof said vertical surfaces.
 7. The semiconductor structure of claim 6,further comprising gate spacers having outer sidewalls that adjoin upperportions of said vertical surfaces.
 8. The semiconductor structure ofclaim 7, wherein said adsorbed fluorine layer contiguously covers alower portion of each of said outer sidewalls of said gate spacers. 9.The semiconductor structure of claim 1, further comprising a buriedinsulator layer located underneath said semiconductor material layer.10. The semiconductor structure of claim 9, wherein a bottommost surfaceof said trench is vertically spaced from a topmost surface of saidburied insulator layer.
 11. The semiconductor structure of claim 1,further comprising at least one gate spacer located on a top surface ofsaid semiconductor material layer.
 12. The semiconductor structure ofclaim 11, wherein said at least one gate spacer comprises: a first gatespacer located at one side of said trench and not overlying said trench;and a second gate spacer located at another side of said trench and notoverlying said trench.
 13. The semiconductor structure of claim 11,wherein a periphery of said vertical surfaces of said trench coincideswith outer peripheries of said at least one gate spacer at which outersidewalls of said at least one gate spacer contact said top surface ofsaid semiconductor material layer.
 14. The semiconductor structure ofclaim 11, wherein each of said at least one gate spacer laterallysurrounds a gate structure comprising a vertical stack, from bottom totop, of a gate dielectric, a gate conductor, and a dielectric cap. 15.The semiconductor structure of claim 11, wherein said at least one gatespacer comprises a material selected from silicon nitride, siliconoxynitride, and a combination of silicon oxide and silicon nitride. 16.The semiconductor structure of claim 1, wherein said semiconductormaterial layer comprises a semiconductor material selected from silicon,germanium, silicon-germanium alloy, silicon carbon alloy,silicon-germanium-carbon alloy, gallium arsenide, indium arsenide,indium phosphide, III-V compound semiconductor materials, II-VI compoundsemiconductor materials, organic semiconductor materials, and othercompound semiconductor materials.
 17. The semiconductor structure ofclaim 1, wherein said semiconductor material layer comprises a singlecrystalline material.
 18. The semiconductor structure of claim 1,wherein a bottom surface of said trench has a crystallographicorientation that provides a greater oxidation rate for a semiconductormaterial of said semiconductor material layer than crystallographicorientations of said vertical surfaces of said trench.
 19. Thesemiconductor structure of claim 18, wherein said semiconductor materiallayer is a single crystalline silicon layer and said bottom surface ofsaid trench has a <111> orientation, and said vertical surfaces of saidtrench has a <110> orientation.
 20. The semiconductor structure of claim18, wherein said semiconductor material layer is a single crystallinesilicon layer and said bottom surface of said trench has a <110>orientation, and said vertical surfaces of said trench has a <100>orientation.